module baudgen(input clk, rst, iorw, iocs, 
			input [1:0] ioaddr, 
			input [7:0] divin, 
			output transrateen,
			output recvrateen);
	
	reg [15:0] divisor;
	reg [15:0] counter;
	reg [3:0] transcounter;
	
	always @(posedge clk) begin
		if (rst)
			divisor <= 16'd32;
		else begin
			if (ioaddr[1] & ~iorw & iocs) begin
				if (ioaddr[0])		//load the divisor 
					divisor[15:8] <= divin;
				else
					divisor[7:0] <= divin;
			end
		end
	end

	always @(posedge clk) begin
		if (rst)
			counter <= 16'd0;
		else begin
			if (counter == divisor)
				counter <= 16'd0;
			else
				counter <= counter + 1;
		end
	end
	always @(posedge clk) begin
		if(rst)
			transcounter <= 4'd0;
		else if(counter == divisor) begin
			transcounter <= transcounter + 1;
		end
	end
	
	assign recvrateen = (counter == divisor);
	assign transrateen = (counter == divisor) & (transcounter == 4'd15);		


endmodule
